1. FIELD OF THE INVENTION
The present invention is in the field of integrated circuit fabrication. In particular the present invention is in the field of high density capacitors in semiconductor chips.
2. BACKGROUND ART
Semiconductor chips comprise both digital circuits and analog circuits. Digital circuits have different capacitance requirements than analog circuits. Due to the slowing effects of unwanted parasitic capacitance, digital circuits on the semiconductor chip generally require low capacitance. In contrast, analog circuits on the semiconductor chip need capacitors with high capacitance density. Thus, for digital circuits there is a drive to decrease capacitance while for analog circuits there is a need to increase the capacitance density.
Device engineers seeking to increase capacitance density in analog circuits on the semiconductor die may attempt to do so in several ways. It is well known that the capacitance value of a parallel plate capacitor is calculated by the equation:C=(ε0εrA)/d  (Equation 1)where ε0 is the permittivity of the free space (ε0=8.85×10−14 F/cm), εr is the relative permittivity (also referred to as dielectric constant or “k”), A is the surface area of the capacitor plate and d is the thickness of the dielectric layer.
Device engineers seeking to gain a higher capacitance density on the semiconductor die for use in analog circuits can do so, based on Equation 1, by increasing the area (A in Equation 1) of the capacitor plates, by reducing the thickness of the dielectric between the capacitor plates (d in Equation 1), or by increasing the relative permittivity of the dielectric material used between the capacitor plates (εr in Equation 1, also known as dielectric constant or “k”).
Due to process limitations, the limited surface area of the semiconductor die, and increased fabrication and manufacturing costs, design engineers can only reduce d or increase A to a limited extent. Therefore, to attain a higher capacitance density on the semiconductor die for analog circuits design engineers have used relatively high dielectric constant materials for the inter-layer dielectrics used in the semiconductor die.
While the use of high dielectric constant materials in the semiconductor die facilitates the fabrication of capacitors with high capacitance density and is therefore desirable for analog circuits, for digital circuits in the semiconductor chip the use of high dielectric constant dielectric has many disadvantages. One of the disadvantages for digital circuits is an increase in the inter-line coupling capacitance between metal lines. Such capacitance causes “noise” or “crosstalk” between metal lines.
Another disadvantage is the increase in capacitance between different layers of interconnect and also an increase in capacitance between a layer of interconnect to the substrate. It is known in the art that a higher capacitance will increase the interconnect metal line delay, i.e. the “RC” delay. Another disadvantage is the significant increase in power consumption resulting from the higher capacitance since the amount of power consumed is directly proportional to the capacitance.
Thus it is seen that there are conflicting requirements for digital and analog circuits in the semiconductor chip. While analog circuits require capacitors to be fabricated at high capacitance density, digital circuits do not require capacitors as part of the circuit and as such low capacitance is desirable for digital circuits for the reasons stated above. However, the use of a low dielectric constant (“low-k”) materials in semiconductor die fabrication to generally decrease capacitance and avoid the disadvantages to digital circuits detailed above runs counter to the need to fabricate high density capacitors for use in the analog circuits.
Device engineers have used metal-insulator-metal (“MIM”) and metal-insulator-semiconductor (“MIS”) capacitors in semiconductor dies. However, in a process utilizing low dielectric constant dielectrics, it is difficult to achieve a high density MIM or MIS capacitor because of the low dielectric constant of the dielectrics used and also because additional process steps and an extra mask may be required.
Another method that can be used to overcome the conflicting capacitance requirements of digital and analog circuits is to construct one dielectric layer which has a low dielectric constant and has all the advantages discussed above for the digital circuits and another separate layer which has a high dielectric constant and is suitable for fabrication of high density capacitors for analog circuits. However, this leads to increased fabrication costs and may not even be attainable with today's fabrication techniques. It would be very desirable to fabricate both digital and analog circuits using the same dielectric material while ensuring a low capacitance for the digital circuits and a high capacitance density for the analog circuits.
Thus, it can be seen that there is a serious need in the art for a way to achieve high density capacitors for the analog areas of a semiconductor die while at the same time achieving a low capacitance digital area.